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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. june 2009 doc id 15585 rev 2 1/39 39 VIPER25 off-line high voltage converters features 800 v avalanche rugged power section quasi-resonant (qr) control for valley switching operation standby power < 50 mw at 265 vac limiting current with adjustable set point adjustable and accurate overvoltage protection on-board soft-start safe auto-restart after a fault condition hysteretic thermal shutdown applications adapters for pda, camcorders, shavers, cellular phones, cordless phones, videogames auxiliary power supp ly for lcd/pdp tv, monitors, audio systems, computer, industrial systems, led driver, no el-cap led driver, utility power meter smps for set-top boxes, dvd players and recorders, white goods description the device is an off-line converter with an 800 v rugged power section, a pwm control, double levels of overcurrent protection, overvoltage and overload protections, hysteretic thermal protection, soft-start and safe auto-restart after any fault condition removal. burst mode operation and device very low consumption helps to meet the standby energy saving regulations. the quasi- resonant feature reduces emi filter cost. brown- out and brown-in function protects the switch mode power supply when the rectified input voltage level is below the normal minimum level specified for the system. the high voltage start-up circuit is embedded in the device. figure 1. typical topology so - 16 dip-7 so16 narrow %5 =&' '5$,1 *1' 9'' )% 6)0%2 '&2xwsxw9rowdjh '&,qsxw9rowdjh !-v table 1. device summary order codes package packaging VIPER25ln / VIPER25hn dip-7 tube VIPER25hd / VIPER25ld so16 narrow tube VIPER25hdtr / VIPER25ldtr tape and reel www.st.com
contents VIPER25 2/39 doc id 15585 rev 2 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 high voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3 power-up and soft start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 power-down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5 auto-restart operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.6 quasi-resonant operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.7 frequency foldback function and valley sk ipping mode . . . . . . . . . . . . . . 20 7.8 double blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.9 starter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.10 current limit set point and feed-forward option . . . . . . . . . . . . . . . . . . . . . 23 7.11 overvoltage protection (ovp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.12 summary on zcd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.13 feedback and over load protection (olp) . . . . . . . . . . . . . . . . . . . . . . . . 27 7.14 burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 29 7.15 brown-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.16 2nd level overcurrent protection and hiccup mode . . . . . . . . . . . . . . . . . . 31
VIPER25 contents doc id 15585 rev 2 3/39 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
block diagram VIPER25 4/39 doc id 15585 rev 2 1 block diagram figure 2. block diagram 2 typical power 3500,9 56,/ 4(%2-!, 3(54$/7. :#$ '.$ ,/')# )start up )nternal3upplybus 2eference6oltages $2!). /3#),,!4/2 34!24%2&2%1#,!-0 ,%" 6$$ 2 3 1 &" $%-!' ,/')# 3 2 1 56,/ 6in?/+ /40 /40 2 sense "2 6 ?! 6in?/+ 2 2 /#0 /60$%4%#4)/. ,/')# /60 3/&4 34!24 /60 "5234 -/$% ,/')# "5234 "5234 (6?/. (6?/. /#0 n d /#0 ?! 07- ,/')# !-v table 2. typical power part number 230 v ac 85-265 v ac adapter (1) 1. typical continuous power in non ventilated enclosed adapter measured at 50 c ambient. open frame (2) 2. maximum practical continuous power in an open fr ame design at 50 c ambient, with adequate heat sinking. adapter (1) open frame (2) VIPER25 18 w 24 w 10 w 13 w
VIPER25 pin settings doc id 15585 rev 2 5/39 3 pin settings figure 3. connection diagram (top view) note: the copper area for heat dissipation has to be designed under the drain pins. '.$ $2!). $2! ). $2! ). '. $ '.$ :#$ 6$ $ &" $2!). .# .# .# .# '. $ "2 '.$ &" :#$ 6$$ $2!). $2!). "2 !-v table 3. pin description pin n. name function dip-7 so16 1 1...4 gnd this pin represents the device gr ound and the source of the power section. 25vdd supply voltage of the control section. this pin also provides the charging current of the external capacitor during start-up time. 36zcd this is a multifunction pin. 1. input for the zero current detecti on circuit for transformer demagnetization sensing. (i.e. r lim , r ff , r ovp and d ovp , figure 31 ) 2. user defined drain current limit set-point and voltage feed forward.the resistor, r lim , connected between zcd pin and gnd causes the current i zcd and then it limits the stat ic maximum drain current. 3. the resistor r ff , between zcd pin and the auxiliary winding, performs the feed-forward operation and then the drain current limitation changes according to the converter input voltage. 4. output overvoltage protection. a voltage exceeding v ovp threshold (typ 4.2 v, see table 8 on page 8 ), shuts the ic down reduci ng the device consumption. this function is strobed and digita lly filtered for high noise immunity. 47fb control input for duty cycle control. in ternal current generator provides bias current for loop regulation. a voltage below 0.5 v (v fbbm + v fbbmhys , see ta bl e 8 on page 8 and figure 35 ) activates the burst-mode operation. a level close to 3.3 v means that we are approaching the cycle-by-cycle over-current set point. 58br brownout protection input wi th hysteresis. a voltage below 0.45 v shuts down (not latch) the device and lowers t he power consumption. device operation restarts as the voltage exceeds v brth plus hysteresis voltage. it can be connected to ground when not used. 7,8 13...16 drain high voltage drain pin. the built-in high vo ltage switched start-up bias current is drawn from this pin too. pins connected to the metal frame to facilitate heat dissipation.
electrical data VIPER25 6/39 doc id 15585 rev 2 4 electrical data 4.1 maximum ratings 4.2 thermal data table 4. absolute maximum ratings symbol pin (dip7) parameter value unit min. max. v drain 7, 8 drain-to-source (ground) voltage 800 v e av 7, 8 repetitive avalanche energy (limited by t j = 150 c) 5mj i ar 7, 8 repetitive avalanche current (limited by t j = 150 c) 1.5 a i drain 7, 8 pulse drain current 3 a v zcd 3 control input pin voltage (with i zcd = 1 ma) -0.3 self limited v v fb 4 feedback voltage -0.3 5.5 v v br 5 brown-out input pin voltage (with i br = 0.5 ma) -0.3 self limited v v dd 2 supply voltage (i dd = 25 ma) -0.3 self limited v i dd 2 input current 25 ma p tot power dissipation at t a < 40 c (dip-7) 1 w power dissipation at t a < 60 c (so16n) 1 w t j operating junction temperature range -40 150 c t stg storage temperature -55 150 c table 5. thermal data symbol parameter max. value so16n max. value dip7 unit r thjp thermal resistance junction pin (dissipated power = 2 w) 20 40 c/w r thja thermal resistance junction ambient (dissipated power = 2 w) 50 100 c/w r thja thermal resistance junction ambient (1) (dissipated power = 2 w) 1. when mounted on a standard si ngle side fr4 board with 100 mm 2 (0.155 sq in) of cu (35 m thick) 40 80 c/w
VIPER25 electrical data doc id 15585 rev 2 7/39 4.3 electrical characteristics (t j = -25 to 125 c, v dd = 14 v; unless otherwise specified) table 6. power section symbol parameter test cond ition min. typ. max. unit v bvdss break-down voltage i drain = 1 ma, v fb = gnd t j = 25 c 800 v i off off state drain current v drain = max rating, v fb = gnd 60 a r ds(on) drain-source on state resistance i drain = 0.2 a, v fb = 3 v, v br = gnd, t j = 25 c 7 i drain = 0.2 a, v fb = 3 v, v br = gnd, t j = 125 c 14 c oss effective (energy related) output capacitance v drain = 0 to 640 v 40 pf table 7. supply section symbol parameter test condition min. typ. max. unit voltag e v drain _start drain-source start voltage 60 80 100 v i ddch start-up charging current v drain = 120 v, v br = gnd, v fb = gnd, v dd = 4 v -2 -3 -4 ma v drain = 120 v, v br = gnd, v fb = gnd, v dd = 4 v after fault. -0.4 -0.6 -0.8 ma v dd operating voltage range after turn-on 8.5 23.5 v v ddclamp v dd clamp voltage i dd = 20 ma 23.5 v v ddon v dd start-up threshold v drain = 120 v, v br = gnd, v fb = gnd 13 14 15 v v ddoff v dd under voltage shutdown threshold 7.588.5v v dd(restart) v dd restart voltage threshold v drain = 120 v, v br = gnd, v fb = gnd 44.55 v current i dd0 operating supply current, not switching v fb = gnd, f sw = 0 k h z , v br = gnd, v dd = 10 v 0.9 ma i dd1 operating supply current, switching v drain = 120 v, 3.5 ma i dd_fault operating supply current, with protection tripping 400 a i dd_off operating supply current with v dd < vdd_off v dd = 7 v 270 a
electrical data VIPER25 8/39 doc id 15585 rev 2 (t j = -25 to 125 c, v dd = 14 v; unless otherwise specified) table 8. controller section symbol parameter test co ndition min. typ. max. unit feedback pin v fbolp over load shutdown threshold 4.5 4.8 5.2 v v fblin linear dynamics upper limit 3.2 3.3 3.4 v v fbbm burst mode threshold voltage falling 0.4 0.45 0.6 v v fbbmhys burst mode hysteresis voltage rising 50 mv i fb feedback sourced current v fb = 0.3 v -150 -200 -280 ua 3.3 v < v fb < 4.8 v -3 ua r fb(dyn) dynamic resistance v fb < 3.3 v 14 19 k h fb v fb / i d 26v/a zcd pin v zcdcl_h upper clamp voltage i zcd = 1 ma 5 5.5 6 v v zcda_th arming voltage threshold positive-going edge 0.8 v v zcdt_th triggering voltage threshold negative-going edge 0.6 v i zcd internal pull-up -2 a t blank turn-on inhibit time after mosfet?s turn-off v zcd < 1 v 6.3 s v zcd >1 v 2.5 s current limitation i dlim max drain current limitation v fb = 4 v, i zcd = -10 a t j = 25 c 0.66 0.7 0.74 a t ss soft-start time 3.5 ms t su start-up time 10 t on_min minimum turn on time 220 400 480 ns td propagation delay 100 ns t leb leading edge blanking 300 ns i d_bm peak drain current during burst mode v fb = 0.6 v 160 ma oscillator section f osclim internal frequency limit VIPER25l 122 136 150 khz internal frequency limit VIPER25h 200 225 250 khz f starter starter frequency vfb = 1 v, v zcd < v zcdt_th 1/4 f osclim khz f oscmin vfb = 1 v, v zcd > v zcda_th 1/64 f osclim khz
VIPER25 electrical data doc id 15585 rev 2 9/39 (t j = -25 to 125 c, v dd = 14 v; unless otherwise specified) table 8. controller section (continued) symbol parameter test condition min. typ. max. unit overcurrent protection (2 nd ocp) i dmax second overcurrent threshold 1.2 a overvoltage protection v ovp overvoltage protection threshold 3.8 4.2 4.6 v t strobe overvoltage protection strobe time 2.2 s brown-out protection v brth brown-out threshold voltage falling 0.41 0.45 0.49 v v brhyst voltage hysteresis above v brth 50 mv i brhyst current hysteresis 7 10 a v brclamp clamp voltage i br = 250 a 3 v v en brown-out enable voltage 150 mv v dis brown-out disable voltage 50 mv thermal shutdown t sd thermal shutdown temperature 150 160 c t hyst thermal shutdown hysteresis 30 c
electrical data VIPER25 10/39 doc id 15585 rev 2 figure 4. minimum turn-on time test circuit figure 5. brown-out threshold test circuits figure 6. ovp threshold test circuits 14 v zcd 14 v zcd 10 a (the ovp protection is triggered after four c onsecutive oscillator cycles) 14 v zcd v zcd
VIPER25 typical electrical characteristics doc id 15585 rev 2 11/39 5 typical electrical characteristics figure 7. current limit vs t j figure 8. drain start voltage vs t j figure 9. hfb vs t j figure 10. brown-out threshold vs t j figure 11. brown-out hysteresis vs t j figure 12. brown-out hysteresis current vs t j
typical electrical characteristics VIPER25 12/39 doc id 15585 rev 2 figure 13. operating supply current (no switching) vs t j figure 14. operating supply current (switching) vs t j figure 15. v zcd vs i zcd figure 16. current limit vs i zcd figure 17. power mosfet on-resistance vs t j figure 18. power mosfet break down voltage vs t j 300 350 400 450 500 0.0 50.0 100.0 150.0 200.0 250.0 i zcd ( a) v zcd (mv)
VIPER25 typical electrical characteristics doc id 15585 rev 2 13/39 figure 19. thermal shutdown t sd t t v dd t hyst v ds t j t v dd off v dd on v dd restart
typical circuit VIPER25 14/39 doc id 15585 rev 2 6 typical circuit figure 20. min-features qr flyback application figure 21. full-features qr flyback application ' & 9287 5 5 5 %5 & & ' & *1' 'ry s 5ry s 5 2372 %5 =&' '5 $,1 6285& ( &21752/ 9' ' )% 8 9,3(5 $&, 1 $&, 1 5 7/ ' &9'' 5/,0 & !-v !-v & 5 ' 9287 & 5 5 5 %5 & & ' & *1' '293 5293 5 2372 %5 =&' '5 $,1 6285& ( &21752/ 9' ' )% 8 9,3(5 $&, 1 $&, 1 5 7/ ' &9'' 5/,0 & 5 & 5i i 5
VIPER25 operation description doc id 15585 rev 2 15/39 7 operation description VIPER25 is a high-performance low-voltage pwm controller ic with an 800 v, avalanche rugged power section. the controller includes the current-mode pwm logic and the zcd (zero current detect) circuit for qr operation, the start-up circuitr y with soft-start feature, an oscillator for frequency foldback function, the current limit circuit with adjustable set point, the second overcurrent circuit, the burst mode manageme nt circuit, the brown-out circuit, the uvlo circuit, the auto-restart circuit and the thermal shutdown circuit. the current limit set-point is set by the zcd pin. the burst mode operation guaranties high performance in the stand-by mode and helps in the energy saving norm accomplishment all the fault protections are built in auto-restart mode with very low repetition rate to prevent ic's over heating. 7.1 power section and gate driver the power section is implemented with an avalanche ruggedness n-channel mosfet, which guarantees safe operation within the specified energy rating as well as high dv/dt capability. the power section has a bv dss of 800 v min. and a typical r ds(on) of 20 at 25 c. the integrated sensefet structure allows a virtually loss-less current sensing. the gate driver is designed to supply a controlled gate current during both turn-on and turn- off in order to minimize common mode emi. under uvlo conditions an internal pull-down circuit holds the gate low in order to ensure that the power section cannot be turned on accidentally. 7.2 high voltage startup generator the hv current generator is supplied through the drain pin and it is enabled only if the input bulk capacitor voltage is higher than v drain_start threshold, 80 v dc typically. when the hv current generator is on, the idd_ch current (3 ma typical value) is delivered to the capacitor on the v dd pin. in case of auto-restart mode after a fault event, the idd_ch current is reduced to 0.6 ma, typ. in order to have a slow duty cycle during the restart phase.
operation description VIPER25 16/39 doc id 15585 rev 2 7.3 power-up and soft start-up if the input voltage rises up till the device start level (v drain_start ), the v dd voltage begins to grow due to the i dd_ch current (see table 7 on page 7 ) coming from the internal high voltage start-up circuit. if the v dd voltage reaches v ddon threshold (~14 v) the power mosfet starts switching and the hv current generator is turned off. see figure 23 on page 17 . the ic is powered by the energy stored in the capacitor on the vdd pin, c vdd , until when the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation. c vdd capacitor must be sized enough to avoid fast discharge and keep the needed voltage value higher than v ddoff threshold. in fact, a too low capacitance value could terminate the switching operation before th e controller receives any ener gy from the auxiliary winding. the following formula can be used for the v dd capacitor calculation: equation 1 the t ssaux is the time needed for th e steady state of the auxilia ry voltage. this time is estimated by applicator according to the output stage configurations (transformer, output capacitances, etc.). the VIPER25 internal power mosfet is switched on or according the voltage signal sensed on the zcd pin, or by the internal o scillator. when the converter is just powered and VIPER25 starts switching the output voltage is zero and then the voltage on zcd pin is not high enough to correct arming the zcd circuit. in this condition the power mosfet is switched on by the internal osc illator. according to the VIPER25 version (l or h) the internal oscillator frequency is 136 khz or 225 khz. if no signal comes from zcd circuit, the power mosfet is switched on each 4/fosc seconds. so the firs ts switching cycles are at f osc /4 switching frequency. when the voltage on zcd pin is high enough to arm and trigger the zcd circuit (see relevant section) properly, the switching frequency is no more related (except for the frequency foldback function) to t he internal oscillator but it de pends by the load and the input voltage. two parameters are defined, the soft start-up time (t ss ) and the start-up length (t su ). the t ss is the soft start-up time during which the drain current is increased cycle by cycle up to the drain curr ent limitation while t su is the time during which the device is working at its drain current limitation keeping the feedback voltage at v fb_lin , not allowing to ramp up towards the v fb_olp threshold (see figure 24 ). these two parameters are obtained as a nu mber of oscillator cycles. because each mosfet turn-on the internal oscillator is reset t ss and t su are not exactly defined in terms of ms. considering the worst case the t ss_max and t su_min . are reported in the electrical characteristic. ddoff ddon ssaux ddch vdd v v t i c ? ? =
VIPER25 operation description doc id 15585 rev 2 17/39 figure 22. start-up i dd current figure 23. timing diagram: normal power-up and power-down sequences -4 m a -1 ma -3 m a -2 ma 1 m a 2 ma v ddo ff v ddo n i dd 0 v ds = 120v f sw = 0 khz v dd i dd v dd re sta rt i dd_off i d d_fa ult i ds _ ch_ fa ul t i ds_ c h after fault v cc v drain vcc on vcc off vcc restart t t t t vin v start i charge 3 ma t t power - on power - of f normal operation regulation is lost here v cc vcc on vcc off vcc restart t t t t vin v start i charge 3 ma t t power - on power - of f normal operation regulation is lost here v dd v dd v dd v dd idd_ch
operation description VIPER25 18/39 doc id 15585 rev 2 figure 24. soft-start and start-up phase: timing diagram 7.4 power-down operation at converter power-down, the system loses regula tion as soon as the input voltage is so low that the peak current limit ation is reached. the v dd voltage drops and when it falls below the v ddoff threshold (8 v typical) th e power mosfet is switched off, the energy transfers to the ic interrupted and consequently the v dd voltages decreases, figure 23 on page 17 . later, if the v in is lower than v drain_start (80 v typical), the start-up sequence is inhibited and the power-down completed. this feature is useful to prevent converter?s restart attempts and ensures monotonic output voltage decay during the system power-down. 7.5 auto-restart operation if after a converter power-down, the v in is higher than v drain_start, the start-up sequence is not inhibited and will be activated only when the v dd voltage drops down the v ddrestart threshold (4.5 v typical). this means that the hv start-up current generator restarts the v dd capacitor charging only when the v dd voltage drops below v ddrestart . the scenario above described is for instance a power-down because of a fault condition. after a fault condition, the charging current is 0.6 ma (typ.) instead of the 3 ma (typ.) of a normal start-up converter phase. this feature together with the low v ddrestart threshold (4.5 v) ensures that, after a fault, the restart attempts of the ic has a ve ry long repetition rate and the converter works safely with extremely low power throughput. the figure 25 shows the ic behavioral after a short circuit event. t ss t su soft start start up phase i drain v fb t t v fb o lp v fb_lin
VIPER25 operation description doc id 15585 rev 2 19/39 figure 25. timing diagram: behavior after short circuit 7.6 quasi-resonant operation the control core of the VIPER25 is a current-mode pwm controller with a zero current detection circuit designed for quasi-resonant (qr) operation, a technique that provides the benefits of minimum turn-on losses, low emi emission and safe behavior in case of short circuit. at heavy load the converter operate s in quasi-resonant mode; operation lies in synchronizing mosfet's turn-on to the trans former's demagnetization by detecting the resulting negative-going edge of the voltage across any winding of the transformer. the system works close to the boundary between discontinuous (dcm) and continuous conduction (ccm) of the transformer and as a result , the switching frequency will be different for different line/load conditions (see the hyperbolic-like portion of the curves in figure 26 ). v dd vds v dd on v dd off v ddrest i dd_ch 0.6 ma short circuit occurs here t t t t t rep < 0.03t rep t fb pin 4.8 v 3.3 v v dd vds v dd on v dd off v ddrest i dd_ch 0.6 ma short circuit occurs here t t t t t rep < 0.03t rep t fb pin 4.8 v 3.3 v idd_ch
operation description VIPER25 20/39 doc id 15585 rev 2 figure 26. switching frequency vs output load at medium/ light load, depending also from the converter input voltage the device enters in valley-skipping mode. an internal oscillator, syn chronized to mosfet?s turn-on, defines the maximum operating frequency of the converter. this frequency is set below 150 khz (136 khz typ.) for applications where emi filt ering needs minimizing; a device option is available where the oscillator is set at 22 0 khz for applications where an extended qr operation range is a plus. as the load is r educed, and the switching frequency tends to exceed that of the oscillator, mosfet?s turn-on will not any more occur on the first valley but on the second one, the third one and so on. in this way a ?frequency clamp? effect is achieved (piecewise linear portion in figure 26 ). when the load is extremely light or disconn ected, the converter enters in burst mode operation. decreasing the load will then result in frequency redu ction, which can go down even to few hundred hertz, thus minimizing all frequency-related losses and making it easier to comply with energy saving regulations or recommendations. being the peak current low enough, no issue of audible noise. the above mentioned way of operation is based on the zcd pin. this pin is the input of the zcd circuit which allows the power section to turn-on at the end of the transformer demagnetization. the input signal for the zcd is obtained as a partition of the auxiliary voltage used to supply the device. (see figure 26 ). when the triggering circuit senses a negative-going edge of the signal applied to the zcd pin going below the v zcdtth threshold (typ, 0.6 v), after an internal delay that helps to achieve minimum drain source voltage switch-on (?valley switching?), the power section is turned on. however, to enable power section turn-on, the triggering circuit has to be previously armed by a positive-going edge exceeding the v zcdath threshold (typ, 0.8 v) on the same zcd pin. f 37 0out f /3# )n p ut6olta g e 1uasi 2esonant-ode 6alle y 3ki pp in g -ode "urst-ode 1uasi 2esonant-odewithout frequency&old back&eature !-v
VIPER25 operation description doc id 15585 rev 2 21/39 figure 27. zero current detection circuit and oscillator circuit after the mosfet turn-off, the blanking time, t blank , is generated in order to avoid an erroneous arming and consequently triggering due to the noise, generated by the transformer?s leakage inductance resonance ringing and coupled to the zcd pin. 7.7 frequency foldback function and valley skipping mode in quasi-resonant mode, the switching frequency is not fixed and depends on both the load and the converter?s input voltage. the switching frequency in creases when the load decreases, or when the input voltage mains increases, and vice versa. in principle it could reach an infinite value. to avoid that, the VIPER25 taps the maximum switching frequency of the application thanks to its control logic. application frequency limitation is realized with an internal oscillator switching at 136 khz (typical value) for VIPER25l or at 225 khz (typical value) fo r the VIPER25h.thi s oscillator is synchronized with power mosfet turn-on ever y switching cycle. when the power mosfet is off, if the first negative-going edge voltage of the zcd pin, resulting from transformer?s demagnetization, appears after at least one internal oscillato r cycle has been completed, the mosfet is turned on and the oscillator re-synchronized. otherwise, if the first negativ e-going edge voltage appears before comp leting one oscillator cycle, the signal is ignored. due to the ringing of the drain voltage, the zcd pin will experience another positive-going edge volt age that arms the circuit and a subsequent negative-going edge voltage. again, if this appears before the internal oscillator cycle is complete, it is ignored, othe rwise the mosfet is turned on and the oscillator re- synchronized. in this way, one or more drai n ringing cycles will be skipped (?valley-skipping mode?, see figure 28 ) and the switching frequency w ill be prevented from exceeding f osc . :#$ 6$$ 6 6 4",!.+ $%,!9 -onostable 3% 2% 1 1 'ate $river &rom07-#omparator /3#),,!4/2 ?& /3# 3tarter3ignal & /3# &req&old"ack 2eset/scillator 3tart4",!.+at-/3&%44urnoff '.$ $2!). !uxiliary 7inding ! " # $ % & !-v
operation description VIPER25 22/39 doc id 15585 rev 2 figure 28. drain ringing cycle skipping as the load is progressively reduced when the system operates in valley skipping-mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the off-time of the power mosfet is allowed to change with discrete steps of one ringi ng cycle, while the off-time needed for cycle-by-cycle energy balance could fall in between. thus one or more longer switching cycles will be compen sated by one or more shorter cycles and vice versa. this mechanism is natural and there is no appreci able effect on the converter?s performances and on its output voltage. the operation described so far does not consider the blanking time t blank after power mosfet's turn off. actually t blank does not come into play as long as the following condition is met: equation 2 where d is the mosfet duty c ycle. if this condition is not met, the time during which mosfet's turn-on is inhibited is extended beyond t osc by a fraction of t blank . as a consequence, the maximum switch ing frequency will be a little lo wer than the internal limit set by the oscillator and valley-skipping mode will take place slightly earlier than expected. 7.8 double blanking time the just said blanking time (t blank ) has two values (see table 8 on page 8 ). which value is used is decided cycle by cycle according to the value of the zcd pin voltage, during demagnetization of the transformer in the previous cycle. if v zcd >1v the t blank has the lower value (2.5 s) if v zcd < 1 v t blank has the higher value (6.3 s). actually the voltage on zcd pin is monitored during the t srobe of the ovp (overvoltage protection) function (see relevant section 7.6 on page 19 ).this feature is introduced in order to avoid that, during start-up phase or in output short circuit condition, when the zcd voltage can be below 1 v, the zcd circuit is erroneously trigged leading t he system to work at higher frequency and in continuous mode. in both the above mentioned conditions, the ou tput voltage of the power supply is quite lower than its nominal value and the zcd pin voltage, during transformer demagnetization, has a value close to the arming and triggering thresholds (<1 v). normally this feature doesn?t have impact on converter design; during steady state operations normally the used t blank is the lower one. ? p in = p in' (limit condit ion) p in = p in'' < p in' p in = p in''' < p in'' t v ds t fw t os c t v t on t v ds t osc t v ds t os c sw blank osc blank f t 1 t t 1 d ? ? = ?
VIPER25 operation description doc id 15585 rev 2 23/39 figure 29. double t blank timing diagram figure 29 shows the typical situation at the conver ter start-up, when the output voltage is still low and the zcd voltage can lead to fals e trigger to the zcd ci rcuit and not correct mosfet switch-on. 7.9 starter if the amplitude of the voltage on zcd pin at th e end of one oscillator cycle is smaller than the v zcdath arming threshold, in which case mosfet's turn-on could not be triggered, the system would stop. this is what normally happens during converte r?s start-up or under overload/short circuit conditions. during the converter?s startup phase, the voltage on zcd pin is not high enough to arm the triggering circuit. thus, the converter operates at a fixed frequency, f starter , (see ta bl e 8 on page 8 ). as the voltage develope d across the auxiliary wind ing becomes hi gh enough to arm the zcd circuit, mosfet's turn-on is locked to transformer demagnetization, hence setting up quasi-resonant operation. as protection, in case the zcd voltage is permanently above the threshold v zcdath , the switching frequency is reduce d to the minimum value, f oscmin , (see table 8 on page 8 ). v aux 1v t 0 zc d (pin 3 ) 1. 5 0. 5 t bl a n k c t t t t t t d a t strobe 6. 3 s 2. 5 s f dela y mosfet switched on by the starter quasi resonant oper ation osc f 4 t 0.8v 0. 6 v
operation description VIPER25 24/39 doc id 15585 rev 2 7.10 current limit set point and feed-forward option the VIPER25 is a current mode converter and the drain current is limited cycle by cycle according to the fb pin voltage value that is related with the feedback loop response and the load. when the drain current, sensed by the integrated sense-fe t, reaches the current limitation, after the internal propagation dela y, the mosfet is switched off. the current limitation cannot exceed a certain value (i dlim ) that can be adjusted acting on the current sunk from the zcd pin during mosfet?s on-time. usually a resistor, r lim , connected from zcd pin to ground is used to fix this sunk current and then the peak drain current set-point: the lower the resistor is, the lower i dlim will be. for a qr flyback converter the power capability strongly depends on the input voltage. in wide-range applications at maximum line the power capability can be more than twice the value at minimum line, as shown by the upper curve in the diagram of figure 29 . to reduce this dependence, the i dlim can be reduced according to the input voltage increase (line feed-forward). this can be easily realized with a resistor, r ff (see figure 30 ), connected between the zcd pin and the auxiliary winding. since th e voltage across the auxiliary winding during mosfet?s on-time is proportiona l to the input voltage through the auxiliary- to-primary turns ratio n aux /n p , a current proportional to the in put voltage is sunk from the zcd pin, thus lowering the overcurrent set point. figure 30. typical power capability vs input voltage in quasi-resonant converter?s in order to proper select the value of the resistance r ff ( figure 31 ), once are known the proper overcurrent set points at minimum and at the maximum converter input voltage, we can find from graph of figure 16 the needed current to sink from zcd pin during mosfet on time. using the following approximated formula we can calculate the r ff . equation 3 where: v in_max and v in_min are the maximum and minimum converter rectified input voltage n aux is the primary to auxiliary winding turn ratio i zcd1 , and i zcd2 are the currents needed to sink from the zcd pin, in order to obtain the selected overcurrent se t points, at maximum and minimum flyback input voltage (see figure 6 ). ? v in v inmi n p inli m @ v inmi n 11.522.53 3.54 0.5 1 1.5 2 2.5 system optimally compensated sy s tem not compensated ) i i ( n v v r 2 zcd 1 zcd aux min _ in max _ in ff ? ? ? =
VIPER25 operation description doc id 15585 rev 2 25/39 the r lim value can be calculated from the following formula knowing the r ff value: equation 4 where: v zcd1 and v zcd2 are the zcd pin voltages when the sunk current is i zcd1 and i zcd2 respectively (see figure 5 ). figure 31. zcd pin typical external configuration 7.11 overvoltage protection (ovp) if the voltage applied to the zcd pin exceeds the internal voltage reference v ovp (4.2 v typ. see ta b l e 8 ), for four consecutive cycle in a row, the device interpreters this condition like a fault and stops operation. this feature is the output overvolt age protection. the auxiliary winding, during transformer demagnetization, tracks converter's output voltage through turn ratio see figure 31 . proper selecting the resistor divider that connect zcd pin to the auxiliary winding (r lim and r ovp in figure 31) it is possible to set the overvoltage protection limit. the function is digital filtered and strobed to reduce noise sensitivity and prevent the protection to be erroneously activated. in fact, in order to trip the protection the zcd has to sense the overvoltage for four consecutive switching cycles (digital filter). this special feature uses an internal counter that is re set at mosfet switch on every time the ovp signal is not triggered . the internal ovp block senses the zcd pin voltage for a time interval whose width is of 500ns and starts 2 s (t strobe on ta bl e 8 ) after mosfet turn off. referring to the figure 31 , the resistors divider ratio k ovp will be given by: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? + ? = ff 2 zcd aux max _ in 2 zcd 2 zcd ff 1 zcd aux min _ in 1 zcd 1 zcd lim r v n v i v , r v n v i v max r =&' &rom3ense&%4 $ /60 4o/600rotection 2 && !uxiliary 7inding 2 ,)- 4o07-,ogic 4ransformer demagnetization sensin g /60 3ensing #urrentlimit setpoint 3oftstart 2 /60 $ !58 9'' !-v
operation description VIPER25 26/39 doc id 15585 rev 2 equation 5 equation 6 where: v ovp is the ovp threshold (see table 8 on page 9 ) v out ovp is the converter output voltage value to activate the ovp (set by designer) designer n aux is the auxiliary winding turns n sec is the secondary winding turns v dsec is the secondary diode forward voltage v daux is the auxiliary diode forward voltage r ovp together r lim make the output voltage divider than, fixed r lim, according to the desired i dlim , the r ovp can be calculating by: equation 7 the resistor values will be such that the current sourced and sunk by the zcd pin be within the rated capability of the internal clamp. k ovp v ovp n aux n sec -------------- v outovp v dsec + () v daux ? ? -------------------------------------------------------------------------------------------------- - = k ovp r lim r lim r ovp + ---------------------------------- = r ovp r lim 1k ovp ? k ovp ---------------------- - =
VIPER25 operation description doc id 15585 rev 2 27/39 figure 32. ovp timing diagram 7.12 summary on zcd pin referring to the figure 30 , the circuitry connecte d to the zcd pin enables to implement the following functions: 1. current limit set point 2. line feed-forward compensation 3. output overvoltage protection (ovp) 4. zero current dete ction for qr operation chosen r lim , r ff and r ovp as described in previous paragraphs this function are automatically defined. ta bl e 9 refers to the figure 31 and list the external resistance combinations needed to activate one or more functions associated to the zcd pin. t va u x 3 v t t t s trobe t counter re s et t counter s tatu s t 0 zcd (pin 4) 2 s 0.5 s ovp fault 0 0 0 0 1 1 2 2 0 0 1 1 2 2 3 3 4 0 e r u l i a f p o o l k c a b d e e f e c n a b r u t s i d y r a r o p m e t n o i t a r e p o l a m r o n t 3 v t t t s trobe t counter re s et t counter s tatu s t 0 (pin 4) 2 s 0.5 s ovp fault 0 0 0 0 1 1 2 2 0 0 1 1 2 2 3 3 4 0 e r u l i a f p o o l k c a b d e e f e c n a b r u t s i d y r a r o p m e t n o i t a r e p o l a m r o n t table 9. zcd pin configurations function / component r lim r ovp r ff d ovp i dlim set point see equation 4 required for zcd not required yes ovp 22 k see equation 7 not required yes line feed-forward 22 k required for zcd see equation 3 ye s i dlim set point and ovp see equation 4 with rff = see equation 7 not required yes ovp and line feed-forward 22 k see equation 7 see equation 3 ye s i dlim set point and line feed-forward see equation 4 required for zcd see equation 3 ye s i dlim reduction+ ovp + line feed-forward see equation 4 see equation 7 see equation 3 ye s
operation description VIPER25 28/39 doc id 15585 rev 2 7.13 feedback and over load protection (olp) the VIPER25 is a current mode converter: the feedback pin controls the pwm operation, controls the burst mode and actives the overload protection of the device. figure 33 on page 29 and figure 34 show the internal current mode structure. with the feedback pin voltage between v fbbm and v fblin , (respectively 0.5 v and 3.3 v, typical values) the drain current is sensed and converted in voltage that is applied to the non inverting pin of the pwm comparator. this voltage is compared with the one on the feedback pin through a voltage divider on cycle by cycle basis. when these two voltages are equal, the pwm logic orders the switch off of the power mosfet. the drain current is always limited to i dlim value. in case of overload the feedback pin increases in reaction to this event and when it goes higher than v fblin the drain current is limited to the default i dlim value or the one imposed through a resistor at the zcd pin. at the same time an internal current gener ator starts to charge the feedback capacitor (c fb ) and when the feedback voltage reaches the v fbolp threshold, the converter is turned off and the restart phase is activated with reduced value of i ddch current (0.6 ma typ, see table 7 on page 7 ). during the first start-up phase of the converter, after the soft-start-up time (typical value is 8.5 ms) the output voltage could force the feedback pin voltage to rise up to the v fbolp threshold that switches off the converter itself. to avoid this event, the appropriate feedback network has to be selected according to the output load. more the network feedback fixes the compensation loop stability. the figure 33 on page 29 and figure 34 show the two different feedback networks. the time from the over load detection (vfb = v fblin ) to the device shutdown (vfb = v fbolp ) can be calculating by c fb value (see figure 33 on page 29 and figure 34 ), using the formula: equation 8 in the figure 33 , the capacitor connected to fb pin (c fb ) is used as part of the circuit to compensate the feedback loop but also as element to delay the olp shut down owing to the time needed to charge the capacitor (see equation 8). after the start-up time, 8.5 ms typ value, du ring which the feedback voltage is fixed at v fblin , the output capacitor could not be at its nominal value and the controller interpreter this situation as an over load condition. in this case, the olp delay helps to avoid an incorrect device shut down during the start-up. owing to the above considerations, the olp delay time must be long enough to by-pass the initial output voltage transient and check the over load condition only when the output voltage is in steady state. the output transien t time depends from the value of the output capacitor and from the load. when the value of the c fb capacitor calculated for the loop stability is too low and cannot ensure enough olp delay, an alternative compensation network can be used and it is showed in figure 34 on page 30 . t olp delay ? c fb v fbolp v fblin ? 3 a --------------------------------------- - =
VIPER25 operation description doc id 15585 rev 2 29/39 using this alternative compensation network, two poles (f pfb , f pfb1 ) and one zero (f zfb ) are introduced by the capacitors c fb and c fb1 and the resistor r fb1 . the capacitor c fb introduces a pole (f pfb ) at higher frequency than f zb and f pfb1 . this pole is usually used to compensate the high freq uency zero due to the esr (equivalent series resistor) of the output capacitance of the flyback converter. the mathematical expressions of these poles and zero frequency, considering the scheme in figure 34 are reported by the equations below: equation 9 equation 10 equation 11 the r fb(dyn) is the dynamic resistance seen by the fb pin. the c fb1 capacitor fixes the olp delay and usually c fb1 results much higher than c fb . the equation 8 can be still used to calculate the olp delay time but c fb1 has to be considered instead of c fb . using the alternative compensation network, the designer can satisfy, in all case, the loop stability and the enough olp delay time alike. figure 33. fb pin configuration 1 fb 1 fb zfb r c 2 1 f ? ? ? = () 1 fb ) dyn ( fb fb 1 fb ) dyn ( fb pfb r r c 2 r r f ? ? ? ? + = () ) dyn ( fb 1 fb 1 fb 1 pfb r r c 2 1 f + ? ? ? = from sense fet 4.8v burst pwm control cfb to pwm logic burst-mode references burst-mode logic + - pwm + - olp comparator to disable logic
operation description VIPER25 30/39 doc id 15585 rev 2 figure 34. fb pin configuration 7.14 burst-mode operation at no load or very light load when the voltage on feedback pin falls down 50 mv below the burst mode threshold, v fbbm , power mosfet is not more allowed to be switched on. it can be switched on again if the voltage on feedback pin exceeds v fbbm . the voltage on pwm comparator non inverting internal input, connected to feedback pin th rough a resistive voltage divider, is lower clamped to a certain value leading to a minimum value, of 160 ma (typ.) for the drain peak current. when the load decrease the feedback loop reacts lowering the feedback pin voltage. as the voltage goes 50 mv below v fbbm mosfet stops switching. after the mosfet stops, as a result of the feedback reaction to the energy delivery stop, the feedback pin voltage increases and exceeding v fbbm threshold mosfet the power device start switching again. figure 35 shows this behavior called burst mode. systems alternates period of time where power mosfet is switching to period of time where power mosfet is not switching. the power delivered to output during switching periods exceeds the load power demands; the excess of power is balanced from not switching period where no power is processed. the advantage of burst mode operation is an average switching frequency much lower then the normal operation working frequency, up to some hundred of hertz, minimizing all frequency related losses. figure 35. burst mode timing diagram, light load management 4.8v from sense fet pwm control + - pwm burst to disable logic + - olp comparator to pwm logic burst-mode logic cfb1 rfb1 cfb burst-mode references i ds v fbbm fb t t 50 mv hyster. burst-mode normal - mode normal - mode t t 50 mv hyster. burst-mode burst-mode normal - mode normal - mode normal - mode normal - mode 100
VIPER25 operation description doc id 15585 rev 2 31/39 7.15 brown-out protection brown-out protection is a not-latched shutdown function activated when a condition of mains under voltage is detected. the brown-out comparator is internally referenced to v brth ,0.45 v typ value, and disables the pwm if the voltage applied at the br pin is below this internal reference. under this condition the power mosfet is turned off. until the brown-out condition is present, the vdd voltage continuously os cillates between the v ddon and the uvlo thresholds, as shown in the timing diagram of figure 36 on page 31 . a voltage hysteresis is present to improve the noise immunity. the switching operation is restarted as the volt age on the pin is above the reference plus the before said voltage hysteresis. see figure 36 . the brown-out comparator is provided also with a current hysteresis, i brhyst .with this approach is possible to set the v inon threshold and v inoff thresholds separately, by properly choosing the resistors of the divider connect to the br pin. fixed the v inon and the v inoff levels, with reference to figure 36 , the following relationships can be established for the calculation of the resistors r h and r l : equation 12 figure 36. brown-out protection: br external setting and timing diagram rh rl ac_ok disable + - br 0.1v vinok vcc + - 0.45v 10u hv input bus hv input bus vino k vcc (pin 3) vin on vin off vds vout br 0.45v i brhyst 15 a t t t t t t t hv input bus vino k vcc (pin 3) vin on vin off vds vout 0.45v 15 a t t t t t t t v dd v dd brhyst brth brth inoff brhyst inoff inon brhyst brhyst l i v v v v v v i v r ? ? ? + ? =
operation description VIPER25 32/39 doc id 15585 rev 2 equation 13 for a proper operation of this function, v in on must be less than the peak voltage at minimum mains and v in off less than the minimum voltage on the input bulk capacitor at minimum mains and maximum load. the br pin is a high impedance input connected to high value resistors, thus it is prone to pick up noise, which might alter the off threshold when the converter operates or gives origin to undesired switch-off of the device during esd tests. it is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nf) to prevent any malfunctioning of this kind. if the brown-out function is not used the br pi n has to be connected to gnd, ensuring that the voltage is lower than v dis (see ta b l e 8 ). in order to enable the brown-out function the br pin voltage has to be higher than v en (see ta bl e 8 ) 7.16 2 nd level overcurrent protection and hiccup mode the VIPER25 is protected against s hort circuit of the secondary rectifier, short circuit on the secondary winding or a hard-saturation of flyback transformer. such as anomalous condition is invoked when the drain current exceed 1.2 a typical. to distinguish a real malfunction from a disturbance (e.g. induced during esd tests) a ?warning state? is entered after the first signal trip. if in the subsequent switching cycle the signal is not tripped, a temp orary disturbance is assumed and the protection logic will be reset in its idle state; otherwise if the 2 nd ocp threshold is exceeded for two consecutive switching cycles a real malfunction is assumed and the power mosfet is turned off. the shutdown condition is latched as long as the device is supplied. while it is disabled, no energy is transferred from the auxiliary winding; h ence the voltage on the v dd capacitor decays till the v dd under voltage threshold (v ddoff ), which clears the latch. the start-up hv current gene rator is still off, until v dd voltage goes below its restart voltage, v ddrest . after this condition the v dd capacitor is charged again by 600 a current, and the converter switching restart if the v ddon occurs. if the fault condition is not removed the device enters in auto-restart mode. this behavioral, results in a low-frequency intermittent operation (hiccup-mode operation), with very lo w stress on the power circuit. see the timing diagram of figure 37 . brhyst brhyst l l brhyst brhyst inoff inon h i v r r i v v v r + ? ? =
VIPER25 operation description doc id 15585 rev 2 33/39 figure 37. hiccup-mode ocp: timing diagram vcc v ds i drain vcc rest secondary diode is shorted here t t t i dmax on off vcc rest secondary diode is shorted here t t t i dmax v dd v dd v dd v dd
package mechanical data VIPER25 34/39 doc id 15585 rev 2 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. note: 1 the leads size is comprehensive of the thickness of the leads finishing material. 2 dimensions do not include mold protrusion, not to exceed 0,25 mm in total (both side). 3 package outline exclusive of metal burrs dimensions. 4 datum plane ?h? coincident with the bottom of lead, where lead exits body. 5 ref. poa mother doc. 0037880 table 10. dip-7 mechanical data dim. mm typ. min. max. a 5.33 a1 0.38 a2 3.30 2.92 4.95 b 0.46 0.36 0.56 b2 1.52 1.14 1.78 c 0.25 0.20 0.36 d 9.27 9.02 10.16 e 7.87 7.62 8.26 e1 6.35 6.10 7.11 e 2.54 ea 7.62 eb 10.92 l 3.30 2.92 3.81 m (1)(2) 1. creepage distance > 800 v 2. creepage distance as shown in the 664-1 cei / iec standard 2.508 n 0.50 0.40 0.60 n1 0.60 o (2)(3) 3. creepage distance 250 v 0.548
VIPER25 package mechanical data doc id 15585 rev 2 35/39 figure 38. dip-7 package dimensions
package mechanical data VIPER25 36/39 doc id 15585 rev 2 table 11. so16 narrow mechanical data dim. databook (mm.) min. typ. max. a 1.75 a1 0.1 0.25 a2 1.25 b 0.31 0.51 c 0.17 0.25 d 9.8 9.9 10 e 5.8 6 6.2 e1 3.8 3.9 4 e 1.27 h 0.25 0.5 l 0.4 1.27 k 0 8 ccc 0.1
VIPER25 package mechanical data doc id 15585 rev 2 37/39 figure 39. so16 package dimensions
revision history VIPER25 38/39 doc id 15585 rev 2 9 revision history table 12. document revision history date revision changes 17-apr-2009 1 initial release 09-jun-2009 2 updated application paragraph in coverpage and table 8 on page 8
VIPER25 doc id 15585 rev 2 39/39 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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